Memory Mapping

This page describes the SNES virtual memory space.

Buses

A bus is a shared pathway that circuits inside and outside a computer use to exchange data. The SNES has one 8-bit-wide data bus and two address buses. The address buses are called address bus A and address bus B.

1. Data bus
   8 bits wide, used to exchange data. If you read while no value has been written onto the data bus, the value last written to the bus is returned instead. This is called open bus.

2. Address bus A
   24 bits wide, used together with the read/write lines (/RD and /WR) and two auxiliary lines. This bus is connected to both the cartridge and WRAM.

3. Address bus B
   8 bits wide, used together with the read/write lines (/PARD and /PAWR).
   This bus is connected not only to the cartridge and the expansion port, but also to WRAM, PPU1, PPU2 and the APU. Communication with the PPU and APU goes through this bus.

Memory map

Different kinds of cartridges, such as LoROM and HiROM, are mapped onto address bus A. The cartridge responds only while the /CART signal is active; it can respond to signals on both address bus A and B, but one of them is ignored. Likewise, when a device is connected to the expansion port, it responds to unmapped registers on address bus B.
WRAM is mapped onto address bus A while the /WRAM signal is active, and is also mapped onto address bus B through registers $2180 - $2183.
The APU is mapped at $40 - $7F on address bus B ($2140 - $217F from the CPU), and PPU1 and PPU2 are mapped at $00 - $3F on address bus B ($2100 - $213F from the CPU).
Putting all of this together gives the following memory map. The “Speed” column in this table indicates the memory access speed for that region.
The master clock frequency is 21.47727MHz on NTSC and 21.28137MHz on PAL, and an internal CPU operation cycle always takes 6 master cycles.
A Fast memory access takes 6 master cycles (3.58MHz/ 3.55MHz), a Slow memory access 8 master cycles (2.68MHz/ 2.66MHz), and an XSlow memory access 12 master cycles (1.79MHz/ 1.77MHz).

Notes
[1] The addresses for the internal CPU registers lie outside address bus A, and the CPU ignores the data bus.
[2] Fast when bit 0 of CPU register $420D is set, Slow when it is clear.

LoROM memory map

In the LoROM model, the bus pins A15 and A23 are not connected to the ROM, and bus pins A16-A22 are connected to ROM pins A15-A21.
The A15 pin, which is not connected to the ROM, is usually combined with the /CART and /WR pins: when A15 is High the ROM is selected, and when A15 is Low the SRAM is selected.
Therefore, in the LoROM model, ROM is in principle not mapped into the lower half of each bus bank. In exchange, a large SRAM can be fitted.
As the maximum of 22 address pins implies, the ROM capacity is at most 4MB.
The standard LoROM memory mapping is as follows.

HiROM memory map

In the HiROM model, bus pins A0 through A21 are connected to the ROM in the same order, so 64KB banks can be accessed linearly.
The A22 and A23 pins are not connected to the ROM.
As the maximum of 22 address pins implies, the ROM capacity is at most 4MB.
The standard HiROM memory mapping is as follows.

ExHiROM memory map

The ExHiROM model can carry an additional ROM chip of up to 4MB on top of a 4MB ROM chip.
Bus pin A22 is still not connected to the ROM, but pin A23 is used to select which of the two ROM chips on the cartridge board is active.
When A23 is High, ROM1 is selected, and when it is Low, ROM2 is selected. ROM1 can be FastROM, but ROM2 is limited to SlowROM.
However, because of the memory map, the cartridge header is placed in ROM2, and the lower 32KB of each of the last two banks of ROM2 (physical addresses $7E:0000 - 7FFF and $7F:0000 - 7FFF) cannot be accessed.
The upper 32KB of each of the last two banks of ROM2 (physical addresses $7E:8000 - FFFF and $7F:8000 - FFFF) are mapped to bus banks $3E and $3F.
The standard ExHiROM memory mapping is as follows.

ExLoROM memory map

The ExLoROM model is a non-standard mapping. Like ExHiROM, it can carry an additional ROM chip of up to 4MB on top of a 4MB ROM chip.
Bus pin A15 is still not connected to the ROM, but pin A23 is used to select which of the two ROM chips on the cartridge board is active.
When A23 is High, ROM1 is selected, and when it is Low, ROM2 is selected. ROM1 can be FastROM, but ROM2 is limited to SlowROM.
However, because of the memory map, the cartridge header is placed in ROM2, and the last bank of ROM2 (physical addresses $7F:0000 - FFFF) cannot be accessed.
The standard ExLoROM memory mapping is as follows.